library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cnt100 is
port(rst:in std_logic;clk:in std_logic;cntout1:buffer std_logic_vector(3 downto 0);cntout2:buffer std_logic_vector(3 downto 0));
end entity cnt100;



architecture behav of cnt100 is


begin 
	process(clk,rst)
	
	begin
	
	if rst = '1'then
		cntout2 <= "0000";
		cntout1 <= "0000";
		
	elsif clk'event and clk = '1' then
		if cntout2 = "1001" then 
			cntout2 <= "0000";
			cntout1 <= cntout1 + 1;
			if cntout1 = "1001" then 
				cntout1 <= "0000";
			end if;
		else
			cntout2 <= cntout2 + 1;
		end if;
	end if;
	
	end process;
end architecture behav;



